? semiconductor components industries, llc, 2000 august, 2000 rev. 4 1 publication order number: mc14557b/d mc14557b 1-to-64 bit variable length shift register the mc14557b is a static clocked serial shift register whose length may be programmed to be any number of bits between 1 and 64. the number of bits selected is equal to the sum of the subscripts of the enabled length control inputs (l1, l2, l4, l8, l16, and l32) plus one. serial data may be selected from the a or b data inputs with the a/b select input. this feature is useful for recirculation purposes. a clock enable (ce) input is provided to allow gating of the clock or negative edge clocking capability. the device can be effectively used for variable digital delay lines or simply to implement odd length shift registers. ? 164 bit programmable length ? q and q serial buffered outputs ? asynchronous master reset ? all inputs buffered ? no limit on clock rise and fall times ? supply voltage range = 3.0 vdc to 18 vdc ? capable of driving two lowpower ttl loads or one lowpower schottky ttl load over the rated temperature range maximum ratings (voltages referenced to v ss ) (note 2.) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) 0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 3.) 500 mw t a ambient temperature range 55 to +125 c t stg storage temperature range 65 to +150 c t l lead temperature (8second soldering) 260 c 2. maximum ratings are those values beyond which damage to the device may occur. 3. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14557bcp pdip16 2000/box mc14557bdw soic16 47/rail marking diagrams 1 16 pdip16 p suffix case 648 mc14557bcp awlyyww soic16 dw suffix case 751g 1 16 14557b awlyyww mc14557bdwr2 soic16 1000/tape & reel mc14557bf soeiaj16 see note 1. mc14557bfel soeiaj16 see note 1. 1. for ordering information on the eiaj version of the soic packages, please contact your local on semiconductor representative. soeiaj16 f suffix case 966 1 16 mc14557b alyw
mc14557b http://onsemi.com 2 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 l32 l16 l8 l4 v dd a/b sel q q clock reset l1 l2 v ss a b ce block diagram truth table inputs output rst a/b clock ce q 00 0 b 01 0 a 00 1 b 01 1 a 1x x x 0 q is the output of the first selected shift register stage. x = don't care 12 13 14 1 15 2 9 7 6 5 4 3 11 10 reset clock ce b a a/b select l1 l2 l4 l8 l16 l32 q q v dd = pin 16 v ss = pin 8 length select truth table l32 l16 l8 l4 l2 l1 register length 0 0 0 0 0 0 0 0 0 0 0 1 1 bit 2bi 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 2 bits 3 bits 0 0 0 0 0 0 0 0 1 1 0 1 3 bits 4 bits 0 0 0 0 0 0 0 1 1 0 1 0 4 bi ts 5 bits 0 0 0 0 0 0 1 1 0 0 0 1 5 bits 6 bits 0 0 a a 0 a a 1 a a 0 a a 1 a a 6 bits 1 a a 0 a a 0 a a 0 a a 0 a a 0 a a 33 bit a 1 1 0 0 0 0 0 0 0 0 0 1 33 bits 34 bits 1 0 0 0 0 1 34 bits 1 1 1 1 0 0 61 bits 1 1 1 1 1 1 1 1 0 1 0 1 61 bits 62 bits bi 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 62 bits 63 bits 64 bits 1 1 1 1 0 1 64 bits note: length equals the sum of the binary length control subscripts plus one.
mc14557b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) v dd 55 c 25 c 125 c characteristic symbol v dd vdc min max min typ (4.) max min max unit output voltage a0o level v in = v dd or 0 v ol 5.0 10 15 e e e 0.05 0.05 0.05 e e e 0 0 0 0.05 0.05 0.05 e e e 0.05 0.05 0.05 vdc a1o level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 e e e 4.95 9.95 14.95 5.0 10 15 e e e 4.95 9.95 14.95 e e e vdc input voltage a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 e e e 1.5 3.0 4.0 e e e 2.25 4.50 6.75 1.5 3.0 4.0 e e e 1.5 3.0 4.0 vdc a1o level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 e e e 3.5 7.0 11 2.75 5.50 8.25 e e e 3.5 7.0 11 e e e vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 3.0 0.64 1.6 4.2 e e e e 2.4 0.51 1.3 3.4 4.2 0.88 2.25 8.8 e e e e 1.7 0.36 0.9 2.4 e e e e madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 0.64 1.6 4.2 e e e 0.51 1.3 3.4 0.88 2.25 8.8 e e e 0.36 0.9 2.4 e e e input current i in 15 e 0.1 e 0.00001 0.1 e 1.0 m adc input capacitance (v in = 0) c in e e e e 5.0 7.5 e e pf quiescent current (per package) i dd 5.0 10 15 e e e 5.0 10 20 e e e 0.010 0.020 0.030 5.0 10 20 e e e 150 300 600 m adc total supply current (5.) (6.) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (1.75 m a/khz) f + i dd i t = (3.50 m a/khz) f + i dd i t = (5.25 m a/khz) f + i dd m adc 4. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 5. the formulas given are for the typical characteristics only at 25 c. 6. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l 50) vfk where: i t is in m a (per package), c l in pf, v = (v dd v ss ) in volts, f in khz is input frequency, and k = 0.001.
mc14557b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (7.) (c l = 50 pf, t a = 25 c) characteristic symbol v dd min typ (8.) max unit rise and fall time, q or q output t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns t tlh , t thl 5 10 15 e e e 100 50 40 200 100 80 ns propagation delay, clock or ce to q or q t plh , t phl = (1.7 ns/pf) c l + 215 ns t plh , t phl = (0.66 ns/pf) c l + 97 ns t plh , t phl = (0.5 ns/pf) c l + 65 ns t plh , t phl 5 10 15 e e e 300 130 90 600 260 180 ns propagation delay, reset to q or q t plh , t phl = (1.7 ns/pf) c l + 215 ns t plh , t phl = (0.66 ns/pf) c l + 97 ns t plh , t phl = (0.5 ns/pf) c l + 70 ns t plh , t phl 5 10 15 e e e 300 130 95 600 260 190 ns pulse width, clock t wh(cl) 5 10 15 200 100 75 95 45 35 e e e ns pulse width, reset t wh(rst) 5 10 15 300 140 100 150 70 50 e e e ns clock frequency (50% duty cycle) f cl 5 10 15 e e e 3.0 7.5 13.0 1.7 5.0 6.7 mhz setup time, a or b to clock or ce worst case condition: l1 = l2 = l4 = l8 = l16 = l32 = v ss (register length = 1) t su 5 10 15 700 290 145 350 130 85 e e e ns best case condition: l32 = v dd , l1 through l16 = don't care (any register length from 33 to 64) 5 10 15 400 165 60 45 5 0 e e e hold time, clock or ce to a or b best case condition: l1 = l2 = l4 = l8 = l16 = l32 = v ss (register length = 1) t h 5 10 15 200 100 10 150 60 50 e e e ns worst case condition: l32 = v dd , l1 through l16 = don't care (any register length from 33 to 64) 5 10 15 400 185 85 50 25 22 e e e rise and fall time, clock t r , t f 5 10 15 no limit e rise and fall time, reset or ce t r , t f 5 10 15 e e e e e e 15 5 4 m s removal time, reset to clock or ce t rem 5 10 15 160 80 70 80 40 35 e e e ns 7. the formulas given are for the typical characteristics only at 25 c. 8. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance.
mc14557b http://onsemi.com 5 timing diagram 1bit length: ce = 0 a/b = 1 l1 = l2 = l4 = l8 = l16 = l32 = 0 pw r 50% t wh(cl) t h 50% t su t rem 50% t tlh t thl t phl t phl t plh 90% 50% 10% a input clock reset q v dd v ss v dd v ss v dd v ss v oh v ol 1/f cl
mc14557b http://onsemi.com 6 logic diagram a/b select b a reset clock ce 9 6 7 3 4 5 cr 32 bit 12 l32 cr 2 bit 1 l2 2 l1 cr 1 bit cr 16 bit 13 l16 14 l8 cr 1 bit cr 8 bit 10 11 q q 15 l4 cr 4 bit v dd = pin 16 v ss = pin 8
mc14557b http://onsemi.com 7 package dimensions pdip16 p suffix plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 soic16 dw suffix plastic soic package case 751g03 issue b d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7
mc14557b http://onsemi.com 8 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z soeiaj16 f suffix plastic eiaj soic package case 96601 issue o on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14557b/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk
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